Recently, there has been an increased demand for further reduion in the size, cost, and complexity of electronic circuits used for transmission f analog voice, digital voice, and highspeed data over various types of communicatn channels. This increased demand has resulted in significant improvements in the development of integrated circuits conversion between analog and digital signals and vice versa. Delta-sigma (.DELTA..SIGMA.) converters are known in the art since the early 1960s. .DELTA..SIGMA. converters conveniently employ oversampling techniques. Analog signals y in frequencies bands between f=0 to f=f=f.sub.max are represented as digital signals x by sampling rates F which are higher then the Nyquist rate (2*f.sub.max): EQU F=N*(2*f.sub.max) (1)
with symbol * for multiplication and factor N as an oversampling ratio. .DELTA..SIGMA. converters can be used as analog-to-digital converters (ADC) and as digital-to-analog converters (DAC). For the application of .DELTA..SIGMA. converters and for prior art designs, the following references arc useful:
[1] Nortsworthy, Steven R.; Schreier R.; Temes G. C. (editors): "Delta-Sigma Data Converters: theory, design, and simulation", IEEE Press, Piscataway 1997, ISBN 0-7803-1045-4, especially chapter 8 (pages 244-264) "Delta-Sigma ADCs with Multibit Internal converters", chapter 10 (pages 309-332) "Architectures for .DELTA..SIGMA. DACs", chapter 12 (pages 380-405) "Analog-Circuit Design for Delta-Sigma DACs"; and PA0 [2] Proakis, J. G., Manolakis, D. G.: "Digital Signal Processing", Prentice Hall Upper Saddle River, N. J., 1996, ISBN 0-13-373762-4.
FIG. 1 illustrates a simplified block diagram of digital-to-analog converter 100 (hereinafter converter 100) known in the prior art. Converter 100 comprises sigma-delta modulator 110 (hereinafter modulator 110), delay units 120-n (n=1 to N-1), one-bit digital-to-analog converters 130-n (n=1 to N), and adder 140. N is the above mentioned oversampling ratio. In FIG. 1, converters 130-n are identified by the letters "UE" standing for "unit element", i.e. a one-bit converter. Delay units 120-n form a hift register.
Converter 100 receives digital input signal x at input terminal 101 and provides nalog output signal y at output terminal 102. Input terminal 101 is coupled to input 112 of modulator 110. Modulator 110 is coupled to delay stage 120-1 via line 111. or n=1 to n=(N-2), delay stage 120-n is coupled to delay stage 120-(n+1) via line 121-n. Line 111 is coupled to converter 130-1 and line 121-n is coupled to converter 130-(n+1). Converter 130-n is coupled to adder 140 via line 131-n. Delay units 120-n, converters 130-n, and adder 140 form block 105. In FIG. 1, signals are identified by primed reference numbers corresponding to the reference numbers of the lines and terminals. Modulator 110 receives digital input signal x (101') at input terminal 101 and provides intermediate signal v.sub.1 (111') at line 111. Conveniently, input signal x is a multibit signal and signal v.sub.1 is a stream of single bits. For example, signal v.sub.1 can have binary logical values "1" and "0". Delay stage 120-n receives signal v.sub.n-1 (121'-(n-1) ) at line 121 -(n-1) and provides signal v.sub.n at line 121-n after a delay time T. The delay time T is a reciprocal representation of the sampling rate F: EQU T=1/F. (2)
wherein the slash/stands for division. In terms of the z-transformation (explained for example, in chapter 3 of [2]), signal v.sub.n+1 can be expressed as a multiplication of v.sub.n with the operator z.sup.1 : EQU v.sub.n (z)=z.sup.-1 *v.sub.n-1 (z) (3)
Converter 130-n receives v.sub.n (121'-n) at line 121-n and provides analog signal w.sub.n (131'-n) at line 131'-n. Adder 140 substantially simultaneously receives signals w.sub.1 to w.sub.N and combines them to analog output signal y (102') on output terminal 102.
Various modification of converter 100 are known in the art. Converters 130-n of converter 100 operate at the high sampling rate F. This limits the precision of converter 100 and adds noise.
Preferably, converters 130-1 to 130-N have substantially equal transfer functions. For example, digital signals v.sub.1 ="1" to v.sub.N ="1" cause converters 130-1 to 130-N to provide substantially equal analog signals w.sub.1 to w.sub.N : EQU w.sub.1 .apprxeq.w.sub.2 .apprxeq.w.sub.n w.sub.N (4)
However, manufacturing variations lead to mismatches between converters 130-1 to 130-N. Mismatch is represented by differences .DELTA.w between analog signals w.sub.n, such as: EQU .DELTA.w=w.sub.n -w.sub.n+1 (5)
Such variations are due to, for example, limitations in the lithographic resolution. Differences .DELTA.w are unconvenient, because they cause distortions in the transfer function.
FIG. 2 illustrates simplified spectrum diagram 160 for modulator 110 of prior art converter 100 (FIG. 1). Diagram 160 illustrates the power spectral density (PSD) of signal v.sub.1 on a vertical axis versus increasing frequency f on a horizontal axis. Spectrum representations arc well known in the art. A person of skill in the art is able to measure such spectra without the need for further explanation.
Trace 161 symbolizes the PSD of a signal component of v.sub.1 with useful information, e.g., voice, between f=0 and a maximum frequency f.sub.max Trace 162 symbolizes the PSD of the noise component of v.sub.1, hereinafter "modulator noise". It is known in the art to cancel the modulator noise by filters coupled to output terminal 102. The modulator noise can have substantially constant amplitude for large frequency range (so-called "white noise"). The literature (e.g., [1]) teaches noise shaping technologies. For example, a PSD amplitude can be increased with the frequency f.
The present invention seeks to provide digital-to-analog converters which mitigate or avoid the above mentioned and other disadvantages and limitations of the prior art.